st 16 n10 n channel enhancement mode mosfet 1 2 .0 a stanson technology 120 bentley square, mountain view, ca 94040 u sa www.stansontech.com copyright ?200 9 , stanson corp. st 16 n10 2009. v1 description st 16 n10 is the n - channel logic enhancement mode power field effect transistor which is produced using high cell density, dmos trench technology. the st 12 n10 d has been designed specially to improve the overall efficiency of dc/dc converters using either synchronous or conventional switching pwm controllers. it has been optimized for low gate charge, low r ds(on) and fast switching speed. pin configuration to - 252 part marking y: year code a: date code b: wafer code feature l 100 v/ 1 2 .0 a, r ds(on) = 1 6 0 m t yp @v gs = 10v l super high density cell design for extremely low r ds(on) l exceptional on - resistance and maximum dc current capability l t o - 252 p ackage design
st 16 n10 n channel enhancement mode mosfet 1 2 .0 a stanson technology 120 bentley square, mountain view, ca 94040 u sa www.stansontech.com copyright ?200 9 , stanson corp. st 16 n10 2009. v1 absoulte maximum ratings (ta = 25 unless otherwise noted ) parameter symbol typical unit drain - source voltage vdss 100 v gate - source voltage vgss ?0 v continuous drain current (tj=150 ) ta=25 ta= 100 id 1 2 .0 6 .0 a pulsed drain current idm 5 0 a continuous source current (diode conduction) is 1 5 a power dissipation ta=25 pd 79 w operation junction temperature tj 150 storgae temperature range tstg - 55/150 thermal resistance - junction to ambient r ja 110 /w
st 16 n10 n channel enhancement mode mosfet 1 2 .0 a stanson technology 120 bentley square, mountain view, ca 94040 u sa www.stansontech.com copyright ?200 9 , stanson corp. st 16 n10 2009. v1 electrical characteristics ( ta = 25 unless otherwise noted ) parameter symbol condition min typ max unit static drain - source breakdown voltage v (br)dss v gs =0v,id= 250 m a 100 v gate threshold voltage v gs(th) v ds =v gs ,id= 2 50ua 1 .0 2.5 v gate leakage current i gss v ds =0v,v gs =?0v ?00 na zero gate voltage drain current i dss v ds = 100 v,v gs =0v 25 ua v ds = 80 v,v gs =0v t j = 150 250 on - state drain current i d(on) v ds R 5v,v gs = 10v 5 0 a drain - source on - resistance r ds(on) v gs =10v,i d =1 2 a 16 0 1 8 0 m forward transconductance gfs v ds =5 0 v,i d = 9.0 a 6.4 s diode forward voltage v sd i s = 9 .0 a,v gs =0v 1. 0 v dynamic total gate charge q g v ds = 80 v,v gs = 10v i d 9.0 a 4 5 nc gate - source charge q gs 7 .2 gate - drain charge q gd 2 2 input capacitance c iss v ds = 25 v,v gs =0v f=1mhz 640 pf output capacitance c oss 160 reverse transfer c apacitance c rss 88 turn - on time t d(on) tr v dd = 50 v,r d = 5.5 i d = 9 .0 a,v gen =10v r g = 12 7 .4 ns 2 9 turn - off time t d(off) tf 40 25
st 16 n10 n channel enhancement mode mosfet 1 2 .0 a stanson technology 120 bentley square, mountain view, ca 94040 u sa www.stansontech.com copyright ?200 9 , stanson corp. st 16 n10 2009. v1 typical characterictics
st 16 n10 n channel enhancement mode mosfet 1 2 .0 a stanson technology 120 bentley square, mountain view, ca 94040 u sa www.stansontech.com copyright ?200 9 , stanson corp. st 16 n10 2009. v1 typical characterictics
st 16 n10 n channel enhancement mode mosfet 1 2 .0 a stanson technology 120 bentley square, mountain view, ca 94040 u sa www.stansontech.com copyright ?200 9 , stanson corp. st 16 n10 2009. v1 to - 252 - 2l package outline
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